AUSTIN, Tex. -- After years of process development and testing, the semiconductor industry may soon be making significant progress in identifying a few leading candidates for next-generation low-k dielectrics in fast, low-power consuming copper interconnects. As many as 150 dielectric materials were on the table several years ago, but tests and the need to integrate thin films with copper processing steps have now greatly narrowed the choices for insulators to less than a handful, according to some experts.
International Sematech here has begun a new round of tests to determine how well films with dielectric constants of 3.0 to 2.1 perform in fabricating two layers of copper metal for via chain structures. Earlier this month, Sematech announced completion of the first round of low-k dielectric evaluations, which tested the materials in processing one layer of copper (see March 10 story).
The industry's attempt to find a mainstream material to replace silicon-dioxide as interconnect insulator may get a boost from IBM Corp., which is widely credited for setting the pace and trends in dual-damacene copper processing after disclosing its technology nearly two-and-a-half years ago (see Sept. 22, 1997, story). IBM Microelectronics plans to roll out its approach to low-k dielectrics in copper interconnects this year, and it believes it will again be in a leadership position, said Russ Lange, a fellow in IBM Microelectronics Research, based in Fishkill, N.Y.
Lange won't disclosed how IBM would tackle the complex problem of replacing SIO2 as the dielectric in interconnects, but he assured it would not be fluorinated silicon glass (FSG), or any other intermediate step that slightly lowers the dielectric constant from 4.1 in standard silicon-dioxide. A number of companies are ramping production of early copper devices with FSG and doped silicon-dioxide to reduce capacitance.
"We didn't show the industry what we were doing in copper until we were ready to start aggressively using it," Lange noted. He hinted that there would be a series of low-k dielectric processes phased into copper production during the next several technology generations, as IBM moves to 0.13-micron and below feature sizes.
Two basic groups of low-k dielectrics are battling each other for an early lead, which is critical because leading chip makers are now attempting to settle on the best candidates and drive them down the learning curves as they shrink interconnect features. Spin-on dielectrics are competing with films deposited by chemical vapor deposition (CVD) tools.
Major equipment suppliers, such as Applied Materials Inc. and Novellus Systems Inc., are aggressively pushing their CVD-based low-k dielectrics, while a range of material suppliers are promoting spin-on films and attempting to partner with other tool makers for support. "In the past, the tool purchase dictated the material, but in this case the material will drive the choice of tools," noted Mark McClear, global marketing manager for advanced electronics materials at The Dow Chemical Co., based in Midland, Mich.
"Even six to nine months ago, there were 12 to 15 candidates for low-k dielectrics. Today, you could make the case that the field is down to two or three, but no more than four or five," McClear said. "We think it will be settled this year, probably by Semicon West the world's largest chip production trade show in San Francisco, July 10-12."
Dow has been working with IBM's Almaden Research Center in San Jose to develop a next-generation porous polymeric material that could be used in copper dual-damascene process with a dielectric constant of about 2.0. The development work is partly funded by a $8.6 million grant under the U.S. Advanced Technology Program (ATP), and Dow intends to use the results to introduce a next-generation porous SiLK spin-on dielectric.
Currently, Dow introduced SiLK in 1997 for use in 0.25-micron processes. The existing SiLK resin is expected to serve the market for the next several years, and the new porous SiLK material will be targeted at second-generation 0.13-micron and new 0.10-micron process technologies, McClear said.
The total budget for the porous material research by Dow and IBM is set at about $18 million. A key issue for next-generation low-k dielectrics will be toughness--the ability to withstand the dual-damascene process steps currently embraced by the chip industry. A key challenge is the ability to hold up to high temperatures (well over 400 degrees C) and the mechanical strength to not crack under chemical mechanical planarization (CMP).
McClear contended that the CVD deposited films are too brittle to hold up to process requirements when feature sizes shrink, and dielectric constant requirements dip below 2.5. However, McClear said he can see the dielectric battle coming down to one spin-on material vs. a film deposited by CVD.
Fab equipment rivals Applied and Novellus rarely agree, but this time they both believe CVD dielectrics will win. "Two years ago, the front runner was spin-on, but today the leading materials are Coral from Novellus and Black Diamond from Applied," asserted Wilbert van den Hoek, executive vice president of integration and development at Novellus in San Jose. "One reason is that people would like to keep using their CVD equipment."
Low-k dielectrics continue to be a missing piece in the ultimate next-generation interconnect with copper metal. Some managers have likened the missing low-k dielectric element in interconnect sandwiches to having peanut butter without jelly.
"Copper is moving forward into production with SiO2 or with the intermediate FSG step, but the full benefit of copper is being held back," observed Ashok K. Shinha, president of Applied Materials' Interconnect Systems and Modules Business Group in Santa Clara, Calif. He noted that current copper processes are addressing a range of important interconnect issues, such as improved protection from metal migration when feature sizes are shrunk, but to get to gigahertz and beyond speeds, copper with low-k will be a tremendous boost," he added.
