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LSI Logic, TSMC to collaborate on copper 0.13-micron process
Partnership will also consider joint development in future technology nodes







Silicon Strategies


MILPITAS, Calif. -- LSI Logic Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. today (April 4) announced plans to jointly develop a new version of a 0.13-micron process, which will be based on TSMC's most advanced copper and low-k dielectric technology.

The new copper technology will be modified to include LSI Logic's frontend transistor process modules--which are used to make gates, mixed-signal devices, I/O structures, and other basic circuit elements in the early steps of wafer processing. However, the new process will be mostly built on TSMC's new 0.13-micron copper and low-k dielectric technology, which went into early production late last year.

(CORRECTION: An early version of this story incorrectly reported that the partners would combine LSI Logic's existing low-k dielectric technology with TSMC's copper processes in the new process.)

The new alliance will give LSI Logic its first copper interconnect technology, and it makes available copper-chip foundry services from TSMC, which will use the jointly-developed process to fabricate wafers for the Milpitas company. TSMC plans to put the new process into production by the end of this year. Design libraries for the new process will be available in the next few months, and LSI Logic expects to deliver the first prototypes of customer designs in the third quarter of 2001, using TSMC's fabs.

The new process will also be transferred to LSI Logic's production lines by late 2002 or early 2003. LSI said it will use the new 0.13-micron process to produce leading-edge system-on-chip (SoC) products.

In addition, the two companies said they have agreed to explore collaborative opportunities for next-generation processes in future technology nodes. The partners said they intend to accelerate their development of these nodes ahead of the Semiconductor Industry Association's international technology roadmap.

"This agreement strengthens LSI Logic's process technology and manufacturing roadmap by incorporating the best of both companies' advanced process technologies within LSI Logic's manufacturing facilities," said Joe Zelayeta, executive vice president of worldwide operations in Milpitas.

For TSMC, the agreement will extend its core technology from a 0.13-micron process launched in December, said F.C. Tseng, president of the world's largest silicon foundry company, based in Hsinchu, Taiwan.

The new 0.13-micron process will be made available to LSI Logic's other foundry partner, startup Silterra (Malaysia) Sdn. Bhd. in Kulim. The Malaysian foundry startup has begun shipping its first production wafers using LSI Logic's 0.25-micron process technology (see March 20 story). Under the TSMC agreement, LSI Logic can make the new 0.13-micron process available to Silterra.

"We are pretty open with each other," said Ronnie Vasishta, vice president of technology marketing at LSI Logic, referring to the new agreement with TSMC. "This technology will be used by TSMC's other customers, which obviously could be our competitors. TSMC also understands the current relationship we have with Silterra," he added. "So we have a provision that will allow Silterra to have access to this technology as well."

No money is exchanging hands in the technology alliance. TSMC and LSI Logic are simply swapping technology rights to create a new low-k dielectric, copper process, Vasishta told SBN in an interview today.

"This process will have all copper interconnects--a full eight layers," he said.

Until now, LSI Logic has focused its efforts on low-k dielectric insulators with conventional aluminum metal interconnects, while other chip makers--including TSMC--opted to pursue copper first followed by low-k films.

"Our approach has been to work on a true low-k dielectric first, integrating it with aluminum," Vasishta explained. "Others went to copper first, using either standard-k dielectrics or something close to it, such as FGS fluorinated silicate glass which is in the 3.9 range. However, we took a very aggressive approach to low-k and used a 0.18-micron aluminum process and 3.1-k dielectric.

"No one has combined those two very low-k dielectric films and full-copper interconnects," Vasishta said. "But this new process we are developing with TSMC will use a lot of LSI Logic's frontend technology--mixed signal modules, transistor technologies and I/O capabilities--mapped it into the copper interconnects with low-k dielectrics being developed by TSMC."

Initially, LSI Logic expects to use TSMC foundry fabs for early prototyping and production of customer designs using the new 0.13-micron technology. The process will be transferred to LSI Logic's fab lines "at the end of next year 2002 or early in the following year 2003, he said. After the transfer of the 0.13-micron process, LSI Logic plans to continue to use TSMC as a foundry source for some of its production of customer chip designs.











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