The new roadmap completely updates the industry's 1999 ITRS document, adding another technology node to its 15-year outlook and revising the industry's consensus on the ability to clear future barriers. In addition to chalking up a new 22-nm (0.022-micron) technology node in 2016, this year's revised roadmap calls for development of completely new transistor structures as potential replacements for traditional CMOS devices in the next six-to-nine years.

The 2001 ITRS also warns that transistor-gate lengths in microprocessors could hit some fundamental process limits in just six years because manufacturers have greatly accelerated the physical scaling of those structures using post-lithographic process techniques (see Nov. 28 story).

Other surprises embedded in the new roadmap include the "deceleration" of several key technologies because they are proving to be more difficult to develop, said members of the ITRS committee during a press briefing on Wednesday. In particular, the 2001 technology roadmap pushes out milestones for progress in low-k dielectrics, metal cladding, and junction processes.

The development of low-k dielectric films for new insulators between copper metal interconnects on ICs has been especially difficult and slower than expected, said roadmap committee leaders.

"Unlike practically anything else that we have ever been looking at, the low-k area is one where there are many viable candidates on the table--all at one time," explained Robert Doering, senior fellow at Texas Instruments Inc. and a member of the ITRS International Roadmap Committee. He said the number of low-k dielectric candidates and processing steps has slowed progress as the chip industry tried to replace silicon-dioxide insulators.

Compared to the 1999 roadmap, the 2001 ITRS document pushes out low-k dielectric milestones by up to several years for new materials with k values below 2. The prior roadmap had called for inter-level metal insulators with dielectric constant values of 1.6-to-2.2 in 2005, but the new ITRS "decelerates" those advances with microprocessors with films not pushing below 2 until 2009. Bulk dielectric constants of less than 2 where pushed out from a previous target of 2005 to 2007 because there are no known solutions, according to the "red flag" designation in the technology tables of the new roadmap.

Some roadmap leaders said chip makers have been able to use new design techniques in interconnects to get around the need for ultra-low-k dielectrics in the near future. However, developments continue in pushing dielectric k values lower, and IC makers will jump at the chance of using those films in the future whenever they are ready, according to Doering.

Brick wall now 'porous'

During the press conference, Doering also revisited the concept of a "red brick wall" looming on the horizon--somewhere after 2005--due to major barriers in device shrinks and transistor scaling. In the 1999 roadmap, the industry was expected to hit the wall between 2005 and 2008. That is still the case, but the unsolved problems have shifted through what Doering said was a "porous" red brick wall.

"We can say it is essentially in the same place between 2005 and 2007, but of course it is not 1999 any more," he said. "This is 2001. So, obviously we have moved closer to the red brick wall." Some improvements and solutions in lithography have been identified since 1999, but other areas of R&D have not gone as well as hoped, he added. "Parameters are moving in both directions," he said comparing technology solutions on one side of the red brick wall barrier.

Overall, the new technology roadmap pulls in the timeframe for most major technology nodes by about one year. The 2001 document also recalibrates the basic measurement of each technology node to more accurately depict precise feature sizes in each generation, said Paolo Gargini, chairman of the International Roadmap Committee and a fellow at Intel Corp.

The 2001 ITRS shows the old 100-nm node as 90 nm. The new benchmark changes the 70-nm node to 65 nm, and 50-nm becomes 45 nm, while the 35-nm node is now 32 nm. In the 1999 roadmap, the 100-nm DRAM generation was expected to hit production in 2005, but now the 90-nm node is expected to arrive in 2004. The 70-nm node had been set for 2008, but now the 65-nm generation is slated for 2007 in the new roadmap. What had been the 50-nm node in 2011 becomes the 45-nm node in 2010. The 35-nm DRAM technology generation moves up from 2014 to the new 32-nm node designation in 2013.

Microprocessor and ASIC technologies continue to accelerate faster than DRAM nodes in the 2001 roadmap--as has been the case in previous ITRS editions. Experts drafting the 2001 document believe microprocessor and ASIC technologies will eventually slow from the current two-year cycle to a three-year node cycle, putting those device on the same pace as DRAM developments after 2004.

However, the roadmap committee will continue to monitor developments in the coming year to determine if that assumption holds up. "In the next week at the IEDM International Electron Devices Meeting and VLSI Symposium in the next six months, we will see the accomplishments, and based on those new developments, we will have an opportunity to decide," said Gargini, referring to the 2002 mid-term update of the roadmap which will soon start.

Perhaps the most important addition to the new ITRS document has been a new chapter on emerging transistor device structures--major changes to the basic transistors that will be needed before the end of this decade, according to some experts. The traditional scaling of conventional CMOS transistors will most likely work until 2004, but then problems will begin to surface, said roadmap committee members. Suddenly various structures inside the CMOS transistor no longer will work as needed, resulting in the need for new materials and design concepts, they said.

Within six-to-nine years, the cross-section of transistors will most likely look completely different than today's CMOS devices, said Chenming Hu, chief technology officer at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and a member of the ITRS roadmap committee. He said the 2001 roadmap proposes three major groups of new transistor structures: ultra-thin body SOI (silicon-on-insulator) transistor; band-engineered transistor; and double-gate transistor.

The ultra-thin body SOI transistor will be fabricated in a very thin film of silicon, about 100 angstroms thick. This technique will enable researchers to build much smaller transistors without using special structures, according the ITRS officials.

The band-engineered transistor would introduce new or modified materials for CMOS devices so that electrons could move faster through the circuit. An example of this would be the use of germanium inside CMOS transistors. (Silicon germanium--SiGe--devices exist today, but they are mostly bipolar based and aimed at radio-frequency functions). The band-engineered device would also use mechanical stress in the structure to artificially control and improve the performance of transistors, explained the roadmap committee members.

A third leading candidate was called double-gate transistors. There are several approaches to this type of transistor, including "fin FET" and vertical transistor designs. These approaches essentially place one gate on top of the transistor and one on the bottom. This could be used to eventually reduce the gate lengths in transistors to as small as 9 nm, which is currently the target of the 22-nm node set for 2016. At 9 nm, these gates will only be made up of 30 silicon atoms, noted ITRS committee leaders.