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AMD eyes Dresden as site for 300mm wafer fab








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Dresden, Germany -- Advanced Micro Devices' fab complex here is being considered as the site for a 300mm wafer pilot line sometime in 2003, and ultimately for a production fab a year later, officials here said Tuesday.

Dr. Hans-Raimond Deppe, AMD vice president and general manager of Fab 30, said a supplier base to support 300mm wafer production is already ramping up to serve Infineon Technology's new fab, which is just starting production on the new larger wafer size.

"It's a natural choice to start AMD's 300mm work here," he said, but added many other factors could influence the site selection for the firm's entry into the next generation wafers.

He conceded that the plethora of local governments around the world offering large tax incentives and assistance could determine the ultimate location for AMD's first 300mm wafer fab. Also AMD has announced it will seek a partner to join in the 300mm fab, who also could be influential in the site selection.

Dresden is the sole fab making AMD's higher-end Athlon family of processors, and next year it will be the only fab for the firm's K8 generation of 64-bit Hammer processors. The fab by the end of this month will be running at full capacity at 5,000 8-inch wafer starts a week.

That includes a nearly 25% expansion in clean room space added last year. The fab has space remaining for yet another 20% clean room expansion to meet increased production needs, Deppe said.

The complex here has land available to build a new adjoining fab as large as the present facility, which could be the 300mm wafer plant if AMD management decided, he added.

The Dresden Fab 30 also includes some manufacturing R&D capability, especially in working with new chip processing materials. Deppe said newly installed laboratories here are looking at a variety of new low K dielectric materials for next-generation processors.

"With die shrink, lines become so close together that coupling effects can introduce crosstalk, which can be controlled by using new low K dielectric materials for interconnection layers on the chip."

For competitive reasons, he declined to identify any of the new materials under study.











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