Oki Semiconductor claims to be the first into the market with high-integration chips based on a fully depleted silicon-on-insulator (SOI) design, a technology earmarked by Intel for use in its processors about five years from now.
Oki said it has developed techniques to build transistors on silicon layers 50nm thick with low-resistance source and drain areas. One problem with the thin channels used in fully depleted SOI is that it tends to force up the resistance through the source and drain areas, which in turn slows the device down.
The company has used wafers from French supplier Soitec to build devices for watches powered by solar cells, saying the move to the technology has cut power consumption in the chips by 75%, largely due to a cut in junction capacitance.
Oki moved into SOI production, based on a partially depleted technology, which uses a thicker silicon layer under the transistor, in 1998. The company said it plans to use the fully depleted process in future short-range RF devices by Spring 2003, using the high-resistance substrate to create passive devices on-chip with higher Q factors than conventional silicon.
The company produced research-level digital devices in early 2001 using a 0.2um process.
