Under its new EasyPath program, Xilinx will generate a custom test program for a customer's FPGA design with a minimum order of 5,000 devices for a non-recurring engineering fee of $150,000 to $300,000. Moreover, the company promises to deliver first silicon to customers within two months after finishing a design.

By coming up with a customized test program, Xilinx says it can reduce per-piece costs from 30 percent to 80 percent. By testing just one design "image," the reasoning goes, the defects that fall out side the customer's design no long matter, meaning it can yield more good die per wafer.

The EasyPath program is available today for Xilinx's high-density Virtex-2 devices, specifically the XC2V3000, 4000, 6000 and 8000. Xilinx's latest Virtex-2 Pro devices, which combine high-speed serial I/Os and embedded PowerPCs, will be eligible for the program at a later time.

The higher the device density, the higher the cost savings percentage, the company said. One caveat: a customer's design must be frozen before it is submitted, because Xilinx cannot guarantee that unused portions of an FPGA fabric would be fully functional, the company said.

In a sense, EasyPath borrows an idea from the ASIC world. "The gate array vendors only test the gates that have been routed, not every possible gate and line," said Babak Hedayati, senior director of product solutions marketing at Xilinx. "And we're not testing every single logic resource and interconnect. We're testing only the ones you need."

The company said the low-cost vehicle makes sense for mid- to high-volume orders because FPGA densities have increased to the point where applying a custom test program can substantially reduce cost. The company expects five to 10 percent of its customers will be interested in moving to the volume production vehicle.

Recently, FPGA competitor Altera Corp. started offering its customers a cost-reduction path via a program called HardCopy, which can reduce die size up to 70 percent by changing an FPGA's routing structure through a mask option, Altera said.

Xilinx, however, stressed that EasyPath is not an FPGA-to-ASIC conversion program in the traditional sense because it does not involve reducing die size and mask programming. Xilinx said it will use the same mask set, process technology and package as it would for a standard FPGA.

Advocates of traditional FPGA-to-ASIC conversions are likely to point out that Xilinx's EasyPath program lacks a migration path to a finer process geometry.

But Xilinx said it been down the conversion path before. In the mid-90s, the company started offering customers a conversion program known as HardWire, but later abandoned it when FPGA designs became more dense and it became difficult to meet timing requirements. The company learned that prototyping, verification and certification steps involved in creating a converted device could take as long as six months to a year, Hedayati said.

With EasyPath, the die and packaging are the same as for the standard FPGA used for the prototype, allowing Xilinx to match performance and functionality while guaranteeing 99.9 percent test coverage, the company said. Board and system requalification, therefore, is not needed. What's more, Xilinx said it can start delivering chips in volume six to eight weeks after a customer submits a design.