Then on Tuesday, the Robbinston girls, who had lost only one game all season, played Perry, the team that had handed them their one defeat. And in a squeaker, our girls won the game and the regional championship. Hooray!

Motorola joining STMicro,
Philips in $1.4B R&D effort

Over and over again in recent weeks, there have been new examples of corporate chip strategy of the future. All the big guys, except Intel, which is big enough to do anything by itself, are joining cliques to share R&D costs, which are getting out of hand at most chip companies.

But if U.S. chip makers keep moving down this path, it would seem to me that America's chip makers are going to end up as just another "hollowed-out" industry. U.S. companies might design and market their new chips, but the "heavy lifting" manufacturing would be done in the Far East. I don't like this trend.

Latest example of this shift is Motorola Semiconductor, which is joining the 300-mm wafer-processing R&D alliance of Royal Philips Electronics and STMicroelectronics in Crolles, France. The three companies will form a new five-year alliance to pursue jointly processes from 90-nm to 32-nm at STMicro's 300-mm wafer R&D fab near Grenoble, France.

The alliance--called Crolles2--also will include development and process alignment efforts that will be carried out with Taiwan Semiconductor. Philips, STMicro, and TSMC had just struck an R&D partnership for compatible 90-nm (0.09-micron) and 65-nm (0.065-micron) processes.

"The beauty of this alliance," says Fred Shlapak, president of Motorola Semi, is that it will result in lower development costs for the partners. "For Motorola, this . . . is a critical element of our 'asset-light strategy,'" he points out, referring to its strategy to outsource as much as half of its CMOS chip production to outside foundries.

Motorola brings to the party its silicon-on-insulator and embedded magnetoresistive random access memory technologies as well as its experience in advanced copper interconnect processes. The three companies each will contribute one-third of the alliance's capital expenditures, R&D costs, and wafer load for the fab. Their total investment is estimated to run $1.4 billion by 2005.

(See April 9 story.)

Is Japan's chip industry
beginning to fade away?

I remember back in the "good old days" of the early '80s when "Japan Inc.," that formidable government-industry team, was gaining on the then-dominant U.S. chip industry mostly by the simple expedient of using cheap money to outspend the Americans in building new plants.

That strategy worked for a while--the Japanese chip industry led the world for a few years. But now the Japanese seem to have forgotten the rules. And the "hollowing out" of the Japanese semiconductor industry is continuing as these chipmakers for the second year in a row hold their capital spending to what many observers call dangerously low levels.

The nation's leading IC manufacturers are expected to trim their capital budgets by an average of 1% in the Japanese fiscal year starting in April. While that might not seem like much of a drop, the $5.2 billion that Japan's top 13 chipmakers are expected to spend on new fabs and equipment follows a 63% reduction last year, according to Morgan Stanley Dean Witter.

The lack of sustained capital infusion threatens to drop Japan's semiconductor industry below Taiwan's and make it more difficult for it to compete with China's fast-growing industry, some observers believe. Taiwan's IC industry, on the other hand, is projected to increase its capital expenditures this year by 7% to $5.22 billion, or a little more than Japan will spend this year.

"History tells us that if you don't keep up with technology investments, you inevitably fall behind," says Susan Billat, analyst at Robertson Stephens. "The outlook is that Japan will continue to lose market share in semiconductors, which has already happened as a result of previous capital cutbacks."

If this decline continues, "we could be seeing the first move in a long trend to a Fabless Japan Inc.," says Risto Puhakka, analyst at VLSI Research. "This would have been inconceivable even a few years ago."

But Japan is now consolidating operations. "They're continuing to outsource more chip production to Taiwan, China, and in some cases South Korea, because they can't invest sufficiently in their own fab facilities," Puhakka notes. But he says the cutbacks "will almost certainly hurt Japan when the global market upturn finally comes, because they won't be positioned to take advantage of the opportunity."

(See April 12 story.)

TSMC no longer 'fast follower,'
pushes for 65-nm ICs by 2004

Taiwan Semiconductor, big daddy of the silicon foundry world, "opened the Kimono" this week to show off its technology roadmap and tools for developing its next-generation chips at the 65-nm (0.065-micron) node and beyond. The revelation confirms a strategy we've been talking about for some time: dumping the "fast follower" approach to new chip making technology and pushing out to the "bleeding edge "of IC technology.

The Taiwanese foundry is going all out to ramp up its 65-nm process in the 2004-to-2005 timeframe. This would be only two or three years after it introduces the upcoming 90-nm (0.090-micron) technology, confirm TSMC officials. Actually, TSMC officially unveiled its 90-nm technology only this week.

To get to the 65-nm generation of chips as fast as possible, TSMC plans to insert several of the latest yet-to-be-tested tools into its fabs to build the 65-nm chips. These new systems will include atomic layer deposition and next-generation lithography equipment. Its 65-nm roadmap calls for 157-nm scanners and, surprisingly, electron-beam projection lithography.

TSMC's aggressive process-technology roadmap underscores a massive change underway in the overall status of the foundry industry, points out Calvin Chenming Hu, chief technology officer. Throughout the late 1980s and most of the 1990s, silicon foundries were between three and four technology generations behind leading-edge chip makers such as IBM and Intel, he acknowledges.

But TSMC is no longer in this mode, Hu maintains. At times now, company executives like to boast that the Taiwanese foundry giant has not only caught up with IBM and Intel in new CMOS process technologies, but has surpassed them in some areas. One example is 90-nm designs using multi-project wafers, where TSMC is accelerating this prototyping and expects to offer this service as early as this spring.

(See April 11 story.)

TSMC backs off its drive for
industry process standards

Taiwan Semiconductor really got the industry's attention last fall when it pushed chip makers to standardize on a single "open" 0.10-micron technology. But TSMC's call for process standards met with resistance in the industry--especially among skeptical rivals in the foundry business.

Now the Taiwan foundry has apparently retreated from its efforts to drive process standards by disclosing instead, a new, but less ambitious program this week to promote its own leading-edge technology. It intends to push for a so-called "process alignment" strategy where TSMC and its key customers will form a consensus on a common set of design rules at the 90-nm (0.09-micron) node and beyond, says Genda Hu, marketing vice president of the giant foundry. TSMC is now ruling out initial cooperation with other foundries.

TSMC will no longer promote a "standard foundry process" for the semiconductor industry as a whole, Hu says. "We stopped promoting this as a standard," he acknowledges. The new program will permit chip makers to bring up their products faster at a TSMC fab, reducing design cycles and costs, Hu claims.

NEC, Philips, and STMicroelectronics already have endorsed TSMC's "process alignment" program. More than 10 other integrated device manufacturers (IDMs) and major fabless design houses have endorsed the program as well, according to the foundry giant.

TSMC and its customers won't exchange or give away their chip-manufacturing secrets, according to Hu, but they will form a consensus on common design rules, electrical parameters, and transistor characteristics.

(See April 9 story.)

The run up in DRAM prices
looks to be over--for now

So what the heck is going on with DRAM prices? The picture isn't nearly as bright for firm pricing as it was just a few weeks ago.

Suppliers had steadily raised contract prices since January as lean inventories and product-mix shifts pushed out lead times on mainstream parts and ongoing merger talks between top vendors created uncertainty about future supply levels.

It all began with a late-December run-up on the spot market, which gave major suppliers more price leverage going into 2002, says Grant Johnson, market intelligence manager at Converge. Market gyrations at the beginning of the year, he says, were caused by a perceived shortage of 128-megabit SDRAM parts as early signs indicated a robust PC sell-through and aftermarket memory upgrades in the first quarter.

But the anticipated demand never materialized, Johnson says. "The latest reports from motherboard makers in Taiwan are that PC sales in the second quarter aren't going to be as strong as people were predicting a month ago," he says.

The recent sharp drop in DRAM prices, however, on the open market doesn't necessarily mean a corresponding drop in OEM contract pricing, says memory suppliers eager to defend their recent price hikes. Last week, the price of a 128-megabit, PC133 SDRAM dipped as low as $3.50 in the broker and aftermarket channels at the same time that OEMs were paying $5 each under previously negotiated supply deals.

This disparity has stalled negotiations for second-quarter pricing. But OEM demand has been very strong. DRAM suppliers claim that's because Pentium 4 support for synchronous and double-data-rate DRAM allowed top-tier PC makers to price high-end systems more aggressively and gain market share relative to "clone" PCs, which are heavily dependent on Taiwan's motherboard industry.

Brokers who stockpiled DRAMs on speculation are now forced to drop prices to unload them, notes Peter Schaefer, VP of memory products at Infineon Technology North America. "Six-to-nine months ago, the spot market had more power than today," he says. "Now there's a lot of questions about whether the price you find there is the real price."

(See April 8 story.)

TSMC going all out to be
first to build 90-nm parts

The fight is heating up among chip makers to be the first to get their 90-nm (0.09-micron) process into production. Taiwan Semiconductor, for one, is now accelerating its schedule for building ICs with the next-generation process.

The world's largest silicon foundry aims to stay a step ahead of its foundry rivals, Intel, and the other leading integrated device manufacturers (IDMs). TSMC expects to begin offering 90-nm prototyping services during the second quarter, with "risk production"--or early production--starting in the third quarter. This stage is for early adopters of technology, which often are strategic foundry customers.

TSMC is going all out with this new process. Called Nexsys, it is a "technology that will enable SoCs system-on-a-chip, brags Hu. It features a wide range of process derivatives, ASIC libraries, and intellectual-property (IP) cores for next-generation chip designs. The foundry will start using Nexsys on 200-mm wafers, then swing to 300-mm wafers in the first quarter of 2003.

TSMC surprised observers by deciding to offer silicon-on-insulator (SOI) as an option with the new process for those applications that need higher speeds or lower power than is available with standard silicon.

The foundry giant also plans to offer its CyberShuttle multi-project wafer prototyping services by the second quarter, much faster than had been expected. And by November, The cost-sharing prototyping service will be offered on the larger 300-mm wafers. Multi-project wafers carry a number of chip designs on a wafer to share the cost of photomasks, processing steps, and materials.

First designs based on Nexsys will be high-speed, nine-metal-layer logic technologies that will include copper-interconnects and low-k dielectrics. Then early next year, TSMC will roll out an embedded memory process and then a mixed-signal/RF process. Later in 2003, it will offer a high-speed, low power process.

(See April 9 story.)

Is the 'big mo' back
at Taiwan's foundries

For a while, it looked like the world's two largest silicon foundries had gone off the track in February with their expected recovery. But the outlook looked much better this week as Taiwan Semiconductor and United Microelectronics both reported strong sequential increases in March sales and headed for a business recovery this year.

TSMC's revenues grew 7.1% to $351 million last month from $328 million in February. The world's largest foundry saw a continuing pick-up in unit sales demand, says president Rick Tsai. TSMC's March sales also were 4.5% higher than the year-ago total.

UMC's March sales jumped 26.3% to $130 million from $103 million in February. The strong increase in March snapped a three-month slide in sales for the second largest pure-play chip foundry.

Tsai said While TSMC's first quarter is typically the low point of the year for chip sales, Tsai says revenues grew 8.3% sequentially in the first quarter from the previous three months. Orders from customers for the second quarter of 2002 are expected to exceed first quarter bookings, he says, so TSMC anticipates sequentially higher revenues in the quarter ending June 30.

(See April 9 story.)

TSMC admits problems
with low-k dielectrics

Taiwan Semiconductor became one of the first chip makers this week to concede its shift to low-k dielectrics wasn't going all that well. While it claims to be ramping up successfully its 0.13-micron process, the low-k work has been delayed and it was still wrestling with this end of the new process.

"We would be the first to admit the transition from 0.18- to 0.13-micron technology has been challenging," says Ed Ross, president of TSMC's U.S. subsidiary. But he quickly adds that "TSMC is the only pure-play foundry--I repeat the only foundry--that is fully qualified at 0.13-micron technology."

TSMC was responding to growing concerns that it is still experiencing yield problems with the 0.13-micron technology, which is causing delays in shipping products by its customers. Rumors are still flying that Broadcom, Nvidia, and other TSMC customers are unhappy with TSMC's 0.13-micron chip yields.

Several silicon foundries reportedly are having trouble reaching acceptable yields on their copper-based 130-nm (0.13-micron) processes. In nearly all cases, Asian foundries are not acknowledging these problems publicly, but indications are that 0.13-micron technologies still are in the debug, or "early-learning/yield-improvement" stages.

While TSMC claims it is shipping 0.13-micron parts, officials acknowledge the company still is having some "reliability" issues due to the low-k dielectrics.

(See April 10 story.)

UMC-Infineon venture
delays fab for six months

With companies like Taiwan Semiconductor buying production gear to increase their capacity as the chip business starts looking better, the joint fab venture between United Microelectronics and Infineon Technologies seems to be moving in the opposite direction and slowing down its capacity build up.

The joint venture's 300-mm wafer fab in Singapore has delayed the installation of production equipment from the third quarter to next January. The joint venture, called UMCi, was holding a "topping off" ceremony this week for the giant fab.

The delay means that the UMCi fab will now go into pilot production in the second quarter of 2003--five-or-six months later than originally planned.

This won't be a problem, claims UMC chairman Robert Tsao. "We expect UMCi to be entering production just in time to meet the rising demand for foundry services."

The $3.6 billion UMCi fab was disclosed at the end of 2000, just as the chip downturn was beginning to hit the chip industry. Also owning a piece of the new fab is EDB Investments, subsidiary of the Singapore Economic Development Board. The 300-mm fab is being built in two phases and will have an ultimate capacity of 40,000 wafers per month.

(See April 11 story.)

Persian Gulf emirate
wants to build wafer fab

Now here's one of the strangest combinations I have run into in all my years in the semiconductor industry. Would you believe a Frankfurt foundry startup, backed by a Brandenburg bank, Intel, and Dubai, of all people, will provide technology to the Persian Gulf emirate so that it can start building a fab in two years?

Well, believe it. In fact, Dubai could be the next big player in the foundry business, believes Klaus Wiemer, former TSMC president who is now CEO of the German foundry. Dubai invested in the project because it wants to diversify its economy from one based almost entirely in natural resources. The emirate sees high technology manufacturing as a strong option, he says.

The Dubai Airport Free Zone Authority is a private equity investor in the German foundry, Communicant Semiconductor Technologies. "Dubai is interested in acquiring the know-how of how to manage high-tech manufacture," Wiemer says. "This investment will give them that." Dubai could begin building its first fab in 2004, probably targeting a 0.13um or 90nm process, he adds.

The German foundry, which will specialize in both CMOS and SiGe:C processes, secured backing from Intel and the Investment Bank of the State of Brandenburg in a $325 million funding that Wiemer says will permit the completion of its Frankfurt fab. Intel will take 20% of the new fab's capacity and has an option for 10% more.

Communicant expects to start production at its $1.3 billion Frankfurt fab in September 2003. The German fab already had secured $1 billion in funding before this latest round. One third of it was European regional assistance and two thirds was in European Investment Bank loans guaranteed by the German government.

Located near the German-Polish border, plans for the new foundry were announced a year ago to build ICs with silicon-germanium: carbon technology licensed from the Innovations for High Performance microelectronics institute and CMOS processes from Intel.

(See April 9 story.)

TSMC makes equipment buy
from Applied to boost capacity

Looks like Taiwan Semiconductor is a strong believer that its business is turning around smartly now. To boost its capacity, the Taiwan foundry reportedly has ordered $200 million worth of 200-mm wafer fab equipment from Applied Materials.

TSMC is ordering the production equipment to double its copper-interconnect foundry capacity, observers say. The foundry reportedly will order more production gear from companies such as ASML, KLA-Tencor, Novellus, and Rudolph Technologies.

But these orders don't quite square with the giant foundry's public position. TSMC is ordering and installing 200-mm wafer tools at a time when it publicly is promoting its investments in next-generation 300-mm fabs and technology. A spokesman for the company wouldn't discuss any orders, but did say that TSMC is expanding in fabs for both wafer sizes to meet the growing demand for its foundry services.

TSMC is in the process of upgrading some of its older-generation capacity with more advanced 200-mm tools, according to the TSMC spokesman. "We do plan to purchase some advanced 8-inch equipment in the coming future," he says, to "quickly increase our high-end, 0.15- and 0.13-micron process capacity."

To meet growing demand, TSMC is boosting its fab capacity by reportedly inserting the new, advanced 200-mm tools from Applied in its Fab 6B plant in Hsinchu. WaferTech, its U.S. subsidiary, also is getting new 200-mm tools to fill out its capacity. Right now, WaferTech is primarily making chips on a foundry basis for Nvidia, sources said.

(See April 8 story.)

March was 'turning point'
for Microchip Technology

The market picture is brightening up faster than expected for Microchip Technology. It now expects to report higher-than-expected net sales and earnings for its fiscal fourth quarter ended March 31.

Net sales will run 5% higher than the previous quarter, hitting $148.5 million, the Chandler, Ariz., company says. And earnings per share will hit 19 cents a share, more than 50% higher than the 12 cents per share in the previous quarter and a penny a share higher than analysts were expecting.

"The tone of our business was strong all quarter, with March being an exceptional month," declares CEO Steve Sanghi. "Order visibility substantially improved during the March quarter," he says, "with bookings up approximately 35% from the immediately preceding quarter, and our book-to-bill ratio exceeding parity for the first time in six quarters." Sanghi believes that the improvement in visibility "marks a turning point for Microchip."

Capacity utilization is expected to increase to 80% in the current quarter vs. 70% in the March period. He figures this capacity increase will translate to 51.5% gross margins in the June quarter, up almost 100 basis points from the March quarter, he says.

"We also are increasing our guidance for net sales for the June quarter to approximately $156 million, or up 5% from the March quarter," Sanghi says. Earnings per share are anticipated to be 21 cents, up more than 10% from the March quarter.

(See April 8 story.)

Philips comes out with
'world's smallest IC package'

I'm always a sucker for the world's fastest this or the world's smallest that in the electronics industry. This week's record holder comes from Royal Philips Electronics, which says it has developed the world's smallest IC package. It is described as a depopulated, very-thin quad flat-pack, no-lead package. The DQFN is 75% smaller than the existing thin shrink small-outline package (TSSOP), Philips says, and it has a footprint of 2.5-by-3 mm in a 14-pin configuration.

The new package also provides better heat dissipation and easier board assembly, according to Philips. It incorporates an exposed die paddle, which provides a 20% improvement in heat dissipation over a comparable TSSOP package. And it doesn't require leads, eliminating the problems of bent leads or co-planarity in board attachment, the company claims.

The DQFN package is part of the Dutch company's efforts to develop next-generation products where miniaturization is essential, according to Bruce Potvin, logic marketing head for Philips Semiconductors. First products in the DQFN package will be its hex inverter Schmitt trigger, quad two-input multiplexer, and an octal buffer/line driver. These parts are now being sampled, and full production is scheduled to begin in June.

(See April 8 story.)

We want your feedback, comments, criticisms, or questions. E-mail us at bhenkel@aol.com.

(Click here for last week's Semiconductor Alert!.)