After that, TI intends to qualify its next-generation 90-nm (0.09-micron) process at TSMC and UMC for volume production in the next couple of years, said Bill Aylesworth, senior vice president and the chief financial officer of the Dallas-based company.

The move is part of TI's new plan to lower capital expenditure expenses in the future and to shift a portion of its leading-edge IC products to TSMC and UMC, Aylesworth told SBN on late Monday after briefing financial analysts on TI's improved first-quarter results. The company's revenues increased sequentially by 2% to $1.83 billion in Q1, and TI reached the breakeven point vs. an operating loss of $195 million in Q4 of 2001 (see April 15 story).

During Monday's conference call with analysts, Aylesworth said TI was aggressively pushing ahead with plans to increase its foundry use, and he indicated that the percentage of products from third-party fabs could reach 20% from today's 10% level. Three months ago--during the last quarterly conference call--Aylesworth said TI would turn to silicon foundries for more production, but at the time few details were available (see Feb. 5 story).

But TI is now identifying TSMC and UMC as its new strategic foundry partners, and it is transferring internally developed technologies to those companies for volume production.

"Our foundry partners will be both TSMC and UMC," Aylesworth told SBN in the interview on late Monday evening in Dallas. The goal is to lower the risks and costs in leading-edge technologies as the next recovery cycle takes hold in the semiconductor markets. In fact, TI has reduced its capital spending in 2002 to $800 million from $1.8 billion in 2001, and it has set an internal goal of increasing operating margins to the 30% range vs. just under 25% in the peak of the last boom cycle during 2000.

The qualification of TI's internally developed 0.13-micron technology is "already in process," he told SBN, referring to the new efforts with TSMC and UMC in Taiwan.

"In the second quarter both TSMC and UMC} will qualify our internally developed 0.13-micron process, just as TI has already qualified internally," Aylesworth explained. "We will have both of them up and running by the middle of this year in addition to TI's own internal capacity."

TI's partnership with TSMC and UMC appears to be much different than recently announced alliances between those two foundry giants and other integrated device manufacturers (IDMs). TI will use its own copper-based CMOS processes in TSMC and UMC frontend lines, while other chip makers have struck development partnerships to either "align" processes with those foundries or jointly create new technologies.

For example, UMC and Advanced Micro Devices Inc. are pursuing compatible processes down to the 65-nm (0.065-micron) technology node for a 300-mm joint-venture fab planned in Singapore (see Jan. 31 story). TSMC plans to work with a new three-way partnership between Motorola Inc., Philips Semiconductors, and STMicroelectronics to "align" next-generation processes (see April 12 story).

But TI intends to use its own process technology in strategic foundry agreements so that its IC development teams can tweak performance and take advantage of the company's R&D, according to Aylesworth.

"We have the commitment from TSMC and UMC to use the TI technology exclusively for TI products," he told SBN. "We will continue to have the benefit of using our own process technology, which we can use early on to design products and fine tune development to match our processes.

"We think that will continue to be an advantage for us," he added. The chief financial officer said the Dallas company believes the two large foundry suppliers will be willing to work with TI in this method going forward and use the experience as a learning vehicle as well as a revenue source for state-of-the-art products. TI is not making any investments in TSMC or UMC foundry plants, Aylesworth said.

For TI, the new foundry strategy and a shift to potentially lower cost 300-mm wafers in its own DMOS 6 fab in Dallas are part of an effort to increase the profitability of the company's semiconductor business. The use of foundries at the leading edge will "reduce our capital expenditures and improve our capital utilization throughout each technology node cycle," Aylesworth told analysts, while fielding questions in the conference call on Monday.

"If you look at the last several years, about 10% of our manufacturing capacity has been in foundries," he said. "That could very well double over a period of time with this strategy of sharing the beginning of each technology node."

While TI is preparing qualification of its first leading-edge technologies at TSMC and UMC, the company is also finishing up its work on qualifying its 300-mm wafer fab in Dallas. So far, the wafer runs in that huge fab have not produce revenues, but after qualification is completed with customers at around the middle of the year, TI expects the DMOS 6 plant to begin generating sales. The facility will be ready for production with a capacity of 5,700 wafer starts per month at the end of June, Aylesworth said.

The company recently decided to move ahead with an expansion of tool sets in the 300-mm fab to increase its capacity to 10,000 wafers per month by the end of this year, he said. The new tool installation is part of TI's $800 million capital spending budget this year.

"Revenue from DMOS6 is still basically zero. In the first quarter, we were shipping early product for qualification," he told analysts. "We expect the 1,000-hour qualification cycle at customers to be completed in the June timeframe."