SUNNYVALE, Calif. -- The potential for widespread use of diagonal interconnects in ICs got another major boost today. Lithography giant ASML Holding N.V. announced successful fabrication of test structures on wafers from 0.18-micron design data, using diagonal interconnect lines vs. the traditional right-angled interconnects employed in most commercial chip layouts.
Supporters of the diagonal interconnect concept--called "X Architecture"--said ASML's proof-of-concept wafer exposures will ease concerns about the manufacturing impact of routing ICs with diagonal metal lines, which proponents believe will shrink die area and speed devices with shorter interconnects.
ASML in the Netherlands said it had simulated the lithography performance for 0.18-micron X Architecture design data, and then successfully completed proof-of-concept wafer exposures on a 248-nm scanner with diagonally-oriented 0.25-micron interconnect structures, based on the 0.18-micron design rules.
The development follows other proof-of-concept tests, including photomask production by both laser and electron-beam reticle tools, according to members of the X Initiative, which was launched last June to promote the diagonal interconnect technology. Proponents of diagonal interconnect routing believe the concept could result in smaller die with 30% more chips on a wafer, 20% less power dissipation, and a 10% increase in performance (see June 4 story).
Earlier this year, Toshiba Corp. said it had successfully laid out the first major IC with the X Architecture diagonal interconnect lines for a new 200-MHz RISC processor (see Feb. 6 story), and Toshiba is expected to become the first chip maker to introduce commercial products with the diagonal routing concept.
"It is a five year mission, and we're almost one-year into it, but the progress has been pretty significant to date," said Jan Willis, who is the X Initiative Steering Group facilitator and vice president of business development at Simplex Solutions Inc. "I think most people would now say we have provided many of the answers to the questions being raised last year," she said, referring to ASML's lithography work and reticle production at U.S.-based DuPont Photomasks Inc. and Dai Nippon Printing Ltd. in Japan.
"One of the most frequently asked questions has been whether it is practical to make masks, and the other issue has been if enhancement techniques in fabricating wafers were needed. The answer today at upcoming technology nodes is, no," said the vice president of Simplex, which is promoting diagonal interconnects with its Liquid Routing software.
The next steps in promoting the X Architecture will include the addition of multiple suppliers for technologies and production systems needed to fabricate diagonally routed ICs, Willis said. In design automation, additional work includes optimizing design rules for the diagonal interconnects and inclusion of rule checks and test chips to help further automate the design flow and results.
ASML's experiments, sponsored by the X Initiative and its members, employed X Architecture design data provided by Simplex Solutions and photomasks produced by Dai Nippon Printing. Simulation results were based on ASML's MaskTools LithoCruiser software, which confirmed that existing mask data automation and simulation software could be successfully applied to X Architecture design data to optimize lithographic wafer production results, said officials with the X Initiative. The interconnect layers were exposed using an ASML PAS 5500/750 Deep ultraviolet (DUV) step-and-scan tool.
On the photomask side of the X Architecture puzzle, efforts have been underway to address concerns about the impact of diagonal lines in reticle making. One early concern has been the time it takes to retile tools to create diagonal lines across photomask areas vs. the traditional grid of routing lines, noted Kenneth A. Rygler, former vice president of marketing and strategic planning at DuPont Photomasks who is a founding member of the X Initiative Steering Group.
"You would believe that it would take more figures to describe a diagonal line than a straight line in the X and Y axis," said Rygler, who is consulting for DuPont Photomasks and other operations as president of Rygler Associates Inc. But he said the write times for diagonal lines in chip interconnects have not materially impacted the turnaround cycles.
"The only small problem that was seen at DuPont Photomasks was in database inspection, which required a retraining of the systems to recognize the difference between the diagonal lines and defects," he said. "The more traditional die-to-die inspection of masks was not a problem," he said, referring to a technique, which compares chip areas of photomasks to each other while looking for defects.
--J. Robert Lineback
