It was indeed a pairing of worthy adversaries. In one corner sat SystemC, a design and verification language built on C++ that spanned from concept to implementation in hardware and software. In the other corner was Superlog, an evolutionary design and verification language based on the Verilog hardware description language (HDL,) that drove modeling and test abstraction to new levels.

In a heated and ongoing battle, each claimed its language was superior and would be victorious.

But a funny thing happened on the way to the knockout. Three years after round one commenced, both contenders have been widely adopted. Both have proved to be effective tools for today's engineers, who themselves are battered a bit by continual process-geometry shrinks and the looming challenge of system-on-chip (SoC) design.

Indeed, the two languages are complementary and are often used within the same design environment. How did this happen? The languages were put to use in real design flows, where their practical benefits quickly became apparent and overshadowed the language spat.

SystemC and Superlog have both developed into standards. Co-Design has been working with Accellera and that body's predecessor, Open Verilog International (OVI), since 1999, donating key subsets of Superlog to form the SystemVerilog 3.0 standard. Approved by Accellera in June, the standard is endorsed by such tool providers and users as Synopsys, Mentor and Intel. The Verilog IEEE working group is starting to leverage the standard for the next version of Verilog.

Also in 1999, CoWare co-founded the Open SystemC Initiative (OSCI) with Synopsys. SystemC's latest release, version 2.0.1, is the result of co-development among Cadence, CoWare, Fujitsu, Motorola, STMicroelectronics and Synopsys, with broad adoption by a community of thousands of regular users. OSCI is developing a Language Reference Manual, based on SystemC 2.0.1, as the starting point for formal standardization with the IEEE.

Backers of both now realize that SystemC and SystemVerilog/Superlog are in different spaces. Each has characteristics that appeal to different design realms.

SystemC is fast becoming a favorite with system architects who are defining products at a higher level of abstraction. Those engineers, in turn, hand off the specification to a hardware designer for implementation in Verilog or, frequently, in its more powerful incarnation, SystemVerilog.

SystemC is finding application at the system level, where the design is independent of hardware or software implementation. SystemC's main advantage lies in its ability to handle the co-design and integration of hardware and software by taking a standard software language and adding architectural and system features in the form of open-source C++ classes. That open quality has greatly increased its acceptance by the design community, since a number of tools and techniques based on it are increasingly available and interoperable, and as powerful as a Mike Tyson roundhouse.

An example is the increasing use of SystemC to create virtual prototypes of SoC designs, beginning with simple descriptions at a high level of abstraction and then refining them through to implementation. In SystemC, those virtual prototypes can be simulated faster than in HDL-based co-verification.

When the time comes to hand off to the hardware-design team, SystemVerilog is the ideal choice, since it has successfully extended Verilog to enable abstract design, allowing models to be quickly created and easily debugged. Leveraging Superlog with SystemVerilog allows Verilog-based verification and systems -- as well as SystemC code -- to be tied into the design implementation process, dramatically decreasing the time taken to tape out a modern device with a minimal investment from the design team. Verilog designers take great comfort in Superlog's pedigree too; it was designed by Peter Flake and Simon Davidmann with the involvement of Phil Moorby, the father of Verilog and undisputed heavyweight champion in the HDL arena.

In fact, SystemVerilog incorporates many of the best features of both Verilog and C. It is simple to use and is familiar, while containing a number of features to abstract design and automate testbenches. And because it is a superset of Verilog, it can be easily applied to existing flows.

Verilog will continue to dominate the RTL-to-GDSII design flow. Despite perceptions to the contrary, SystemC was never aimed at changing that. As evidence that C-based design is both production-worthy and complementary to the Verilog flow, consider this: Co-Ware gave away a Sony camcorder at this year's Design Automation Conference. The camcorder contained an SoC designed from concept to register-transfer level (RTL) in CoWare's C-based flow and from RTL down in Verilog.

In an era of conflict, isn't it nice for once to see two worthy opponents enter the ring, shake hands and not come out fighting? The clear winner in this bout appears to be the design community.

Dave Kelf is vice president of marketing at Co-Design Automation Inc. Pete Hardee is director of product marketing at CoWare Inc.