In a talk titled "No exponential is forever, but forever can be delayed," Moore is expected to trace the path taken by semiconductor integration — and answer conjectures that the yearly doubling of transistors per chip may soon reach its twilight. We have at least another decade of exponential growth, he's expected to argue.

Following Moore in the morning plenary session, industry speakers will turn to the theme of this year's conference: power-aware systems. University of Tokyo professor Takayasu Sakurai will dive directly into the power issue by examining the higher device leakage currents prevalent in 90-nanometer CMOS processes and their implication for design. And Bruno Murari, R&D director at the STMicroelectronics facility in Agrate, Italy, will lobby for expanding the process repertoire beyond vanilla CMOS with high-voltage CMOS and mixed-technology processes.

The keynotes, which follow the traditional Sunday tutorials, will begin three days of paper sessions, presenting 188 papers from around the globe — 60 from universities, 128 from industry. Throughout the sessions, this year's conference will return repeatedly to the 50th-anniversary theme, with video clips spotlighting the papers and personalities of the conference's first half-century.

The paper sessions

Surprisingly, given the collapse of the industry, nearly a third of the papers — some 16 percent on wireless and 14 on wireline — deal with communications issues. The majority of wireless papers concern wireless-LAN connectivity (four of them on new architectures for 802.11a, two more on 802.11-Bluetooth combo transceivers). But one paper, from a Philips Research team, describes what's touted as the most highly integrated cable tuner ever. The device uses 30-GHz BiCMOS technology.

The wireline presentations highlight 40-Gbit/second chip sets for OC-768, using such fabrication technologies as silicon germanium, CMOS and indium phosphide. SiGe seems to be regarded as nearly mainstream for these applications.

There is a tradition at ISSCC that analog and mixed-signal technologies show monotonic advances in performance, and this conference will be no exception. Among analog paper submissions, the highlights include a 16-bit D/A converter with a 300-MHz output and an 8-bit A/D converter with a 20-GHz sample rate.

But greater integration and greater data rates won't be the sole focus this year. In accordance with the stated theme, many papers will look closely at the growing issue of power dissipation. Intel researchers, for example, will return to report further progress on the use of body diodes to control leakage currents in extreme-submicron processes. The company had reported in previous years that "sleep transistors" and body bias can be employed to reduce a processor's quiescent current. This year, Intel's Hillsboro, Ore., team has studied the impact of that strategy on performance, counting up the clock cycles necessary to make a sleep transistor truly effective. The number is small and accessible, and the use of the current-stopping devices can effect a 44 percent savings in processor power consumption, the team will report.

A number of papers from Japanese corporations and labs describe work with digital circuits at extremely low operating voltages: down to 0.5 V.

Researchers at NTT, for example, have induced frequency dividers to work at 5.4 GHz at 0.5 V. The same 0.25-micron circuit will work at 3.6 GHz at 0.3 V, they say.

Panels and workshops

As always, the most colorful discussions promise to be at the evening panels. One such session on analog systems-on-chip — provocatively titled "SoC: DOA, or RIP?" — is being organized by Krishnaswamy Nagaraj of Texas Instruments Inc. and will be chaired by David Allstot of the University of Washington. "The technologies best-suited for realizing high-performance analog and RF circuits are different from the technologies that are best suited for highly dense digital circuits," they write. "Future devices — with expected higher gate leakage — will make it very difficult to incorporate sampled-data circuits."

In further attempts to dump the cold water of reality on what can become a research-oriented conference, additional panel sessions will ask whether SoC devices can meet cost specs and whether multichip modules are really the way to go. The panelists will include centrist Bruce Wooley of Stanford University; Ken Hansen, the Motorola vice president who dismissed the single-chip cell phone at ISSCC two years ago; and Texas Instruments' Dennis Buss, who created so much controversy last year with his analysis of 90-nm CMOS leakage-current hazards and remedies.

Equally likely to provoke heated discussion will be the panel on analog intellectual property, "Stairway to SoC Heaven?" Organized by the always acerbic Rudolf Koch of Infineon Technologies, the panel will discuss the potential for reusing analog, mixed-signal and RF cell blocks. The all-star gathering will feature IP generators like Thomas Heydler of Barcelona Design and Jean-Franois Pollet of Dolphin Integration; IP users like Massao Hotta, chief engineer at Hitachi, and Phillippe Magarshack, vice president at STMicroelectronics' R&D Center; and long-term analog visionary Georges Gielen of the Catholic University of Leuven (Belgium).

CMOS advocates are forever examining the commercial potential for their work, and here the single-chip cell phone debate returns with a vengeance. Despite Hansen's assertion that a modern cell phone has about 400 parts, of which ICs account for about 10, at least two ISSCC panels will debate the merits of highly integrated phones and the hurdles they face.

A panel co-organized by Masayuki Mizuno of NEC Corp. and Akira Matsuzawa of Matsushita will project architectures and circuits for mobile phones in the year 2010. There may be little controversy here, considering that Japanese feature phones are already equipped with color screens for gaming and Internet access. But it will be interesting to see how this international panel (including authorities from Europe, Korea, Japan and the United States) assesses the possibility for video, voice recognition and fingerprint identification on upcoming phones. The combative title for the Tuesday evening session is "Future Mobile Phones: A Beautiful Dream or Smoke in LSI Technology?"

Another wireless panel, this one on Sunday evening and organized by William Camp, a senior scientist at Sony Ericsson, will attempt to sort out the problem of integration of RF and baseband components. Panelists will include analog expert Sven Mattisson of Ericsson; James Mielke, systems architect at Motorola; and William Krenik, a wireless architect with Texas Instruments.

Good, bad and ugly

Elsewhere, an evening panel on memory evolution, organized by John Barth of IBM Microelectronics, will serve as a reminder of which memory technologies didn't work, which were successful and which came in between. Featuring Dick Foss, chairman of Mosaid Technologies; consultant Howard Kalter of HLK; and Samsung vice president Changhyn Kim, it's titled "The Good, the Bad, the Ugly."

ISSCC will also feature three highly topical workshops. The first, involving authorities from Intel, IBM, AMD, Hitachi and the University of California at San Diego, will explore pushing the limits of CMOS in new circuits and systems. The second, on microprocessor design on a shoestring power budget, will include engineers from Sun Microsystems, Intel, IBM, ARM and Stanford. The third workshop, focusing on gigahertz radio design, will offer perspectives from UCLA, Infineon, the CMOS-enamored Catholic University of Leuven, an 802.11-bolstered Agere Systems and the megahertz-A/D-obsessed Analog Devices Inc.

Bringing up the rear, with a discussion of CAD tools for analog and mixed-signal design, will be Rob Rutenbar of Carnegie-Mellon University.