SAN FRANCISCO--During the International Solid-State Circuits Conference (ISSCC) here this week, Intel Corp. plans to disclose several technologies that will make good on its promise to deliver 10-GHz or faster microprocessors by the end of this decade.
In separate papers at ISSCC, Intel plans to describe several "building blocks" to enable high-speed, low-power processors. Among the "building blocks" include a 3.5-GHz multiphase clock generator, a 5-GHz floating point multiply and accumulate unit, and so-called "sleep transistors" for use in low-power applications, according to the company.
It also plans to give separate papers on "special-purpose" hardware blocks, such as a TCP/IP offload engine and an 8-gigabit-per-second, simultaneous bi-directional I/O technology designed to boost the speeds of its chip-to-chip bus technology, dubbed PCI Express.
These technologies are not being offered by Intel right now, but they do provide a sneak preview of the company's future roadmap. At present, Intel is shipping chips, based on its 0.13-micron process technology. It is expected to roll out 90-nm chips in late 2003 and 65-nm designs in 2005, according to Intel's roadmap.
By the end of this decade, the company is also expected to develop and ship processors that run at speeds from 10-to-20-GHz. But to enable these high-speed chips, Intel is scrambling to address a major issue: power consumption.
If processors continue to use conventional transistors, then future devices could one day dissipate as much power as a nuclear plant--or even the sun's surface, according to Intel.
In response, Intel has been devising some new and key transistor-level technologies to reduce power consumption. At ISSCC, for example, Intel is expected to give a paper on "sleep transistors" as a possible means to solve the heat problems.
Last year, Intel disclosed plans to incorporate "sleep transistors" onto future-generation microprocessors to push clock frequencies higher and help tame the worsening leakage current that threatens high-speed processor designs. The sleep transistor design style is expected to cut leakage current from tenfold to one-hundredfold (see June 13, 2002 story ).
"It's technology right now," said Shekhar Borkar, Intel Fellow and director of the company's Circuit Research Lab. "Sleep transistors" could reduce "overall power consumption by 10-20%," Borkar said in a press event last week.
On the performance side of the equation, Intel this week at ISSCC will also present a paper on a 5-GHz floating point MAC, which is said to have a sustained performance of five-gigaflops-per-second. Based on 90-nm process technology, the device is a carry-save, single-cycle accumulate floating-point unit, with a 12-stage pipeline.
"In the lab, we can push it to 6-GHz," Borkar said. "This is a special-purpose floating point multiplexar. This is a technology for multimedia applications," he said at the press event.
Intel will also present another paper on a 3.5-GHz, 32-mW multiphase clock generator, which will enable processors at speeds of 10-GHz or faster.
