MUNICH, Germany --- Chipmaker Infineon Technologies AG announced today (March 17, 2002) the development of a series of memory products including: first silicon of Infineon's second generation double data rate (DDR2) memory chip, engineering samples of a 1-Gbyte DDR small outline dual-in-line memory module, a 512-Mbit synchronous DRAM and production of the company's reduced latency DRAM in a 256-Mbit memory capacity.
The DDR2 memory will initially offer data rates per pin of 400-Mbit/s, 533-Mbit/s and 667-Mbit/s. Memory modules designed using the 533-Mbit/s version would have an aggregate bandwidth of 4.3-Gbyte/s.
The chips have been manufactured using a 110-nm manufacturing process technology, configured as quad-bank DRAMs, and will be available in x4, x8 and x 16 organizations. Infineon expects that DDR2 components will appear in end-user systems in 2004.
